mardi 21 avril 2015

How to generate an asynchronous reset in verilog always blocks with chisel

Chisel generate always blocks with only clock in sensivity list :

always @posedge(clk) begin
  [...]
end

Is it possible to configure Module to use an asynchronous reset and generate an always block like this ?

always @(posedge clk or posedge reset) begin
   [...]
end

Aucun commentaire:

Enregistrer un commentaire